Design of Voltage Controlled Oscillator using CMOS 180 nm Technology

Authors

  • Vandana Khanna Department of EECE, The NorthCap University, Gurugram, India
  • Saksham Arora Department of Electrical, Electronics and Communications Engineering, The NorthCap University, Gurgaon, Haryana, India
  • Piyush Yadav Department of Electrical, Electronics and Communications Engineering, The NorthCap University, Gurgaon, Haryana, India

DOI:

https://doi.org/10.37628/ijaic.v5i1.1059

Abstract

In this work, a voltage controlled oscillator (VCO) with sensible one-dimensionality and high gain is designed in 180 nm CMOS technology. The circuit is a modification of the standard ring oscillator. This paper describes the implementation of a Current Starved CMOS voltage controlled oscillator and cascading of its five stages for PLL (Phase Locked Loop). VCO (starved by current) is straightforward ring oscillator containing inverters that are cascaded. The circuit is designed using a 180 nm CMOS technology. By changing the control voltage of the VCO from 0.5 V to 1.8 V, the variation of oscillation frequency from 81.85 MHz-2.433 GHz is earned. Keywords: Voltage controlled oscillator, CMOS, 180 nm

Author Biography

  • Vandana Khanna, Department of EECE, The NorthCap University, Gurugram, India
    Department of Electrical, Electronics and Communications Engineering, The NorthCap University, Gurgaon, Haryana, India

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Published

2019-11-21

Issue

Vol. 5 No. 1 (2019)

Section

Articles