Implementation of Efficient Ladner-Fischer Adder Using Binary Logic
Abstract
A parallel-prefix adder gives the best performance in VLSI design. However, the performance of Ladner–Fischer adder through black cell takes huge memory. So, gray cell can be replaced instead of black cell which gives the efficiency in Ladner–Fischer adder. In efficient Ladner–Fischer adder, addition operation does not wait for previous bit addition operation, and modification is done at gate level to improve the speed and to decrease the memory used. So, here in this paper, we will implement efficient Ladner–Fischer adder using binary logic for high speed.References
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