Vol 2, No 2 (2016)

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Table of Contents

Articles

Design and Analysis of 8T full adder using 77nm Technology
Manisha Agnihotri, Dipti Bichwe
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7-10
Comparative study of a 32 Bit Vedic Multiplier with a Conventional Binary Multiplier
Rohan Muley, Amrita Tuteja
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26-29
Multi-level CMOS LDO-Voltage Circuit with Bi-CMOS LDO with and without Amplifier
Kamlesh Sharma, Gajendra Sujediya, Abdul Naim Khan
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18-25
Temperature Dependent Performance Analysis of SWCNT Bundles as VLSI Interconnects
Shilpa Agrawal, Ankit Kumar, Mayank Kumar Rai, Abhishek Shrivastava
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11-17
ENERGY EFFICIENT LOW-VOLTAGE DYNAMIC COMPARATOR
Sushil Kumar Jain, C Periasamy
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1-6