Study on FPGA Design Process and Physical Design Mapping

Abstract

In supporting hardware debugging in the JHDL design environment, we have found that knowing how design elements from the user’s logical design were mapped to their counterparts in the FPGA physical implementation is quite important. With only a partial mapping from the logical to the physical, we would not be able to provide users of JHDL with a complete view of what their circuit is doing during hardware execution via FPGAs’ readback mechanism. Beyond the applications of debugging, this same knowledge can also be used to provide the designer with a more detailed and understandable view of a circuit once physically implemented and contribute to improved and more understandable analyses of design characteristics such as dynamic power consumption and critical path identification. As background, we will briefly review the role of readback in debugging FPGA circuit designs and why determining the logical to physical mapping is important for debugging hardware with readback. Next, we will discuss the portion of the JHDL design flow which applies to hardware debugging, namely, circuit netlist creation, the processing of Xilinx report files, and the creation of a JHDL readback symbol table. Following this, we will discuss how board models interact with and use the JHDL readback API as well as how FPGA vendor software can improve its support for third party tools which need to determine logical-to-physical design mappings. Lastly, we will describe other possible uses of this mapping information.

Keywords: FPGA, JHDL, Xilin, Simulation, CCMs