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Using of Clock Gating Technique for Power Dissipation Reduction in Sequential Circuits

A. Vijayaprabhu, Vijayaraghavan N, Anushya Devi, Muthamizhan .M

Abstract


Reduced power dissipation, scalability of technology and the requirement for faster performance and more functionality are becoming a critical hurdle for circuit design. VLSI circuits are both combinational and sequential, with the clock being the primary source of dynamic power consumption in sequential circuits. We present a deterministic clock-gating (DCG) technique, which efficiently reduces the power of VLSI circuits, because clock power might be crucial in high-performance VLSI circuits. Clock gating is a technique for reducing clock power usage by turning off idle clock cycles.

A Verilog-based technique is used to insert clock-gating circuit and reduce the dynamic power. This paperdiscusses to reduce the power consumed in the VLSI circuits such as shift register, counters and S27 using clock gated technique andto compare the power dissipated of conventional VLSI circuits and the proposed clock gated circuits.


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References


D. Satyaraj and V. Bhanumathi, “Efficient design of dual controlled stacked SRAM cell,” Analog Integr. Circuits Signal Process., vol. 107, no. 2, 2021, doi: 10.1007/s10470-020-01761-3.

M. Sharma, N. Gupta, and R. Gupta, “POWER REDUCTION TECHNIQUES IN VLSI,” Int. J. Eng. Technol. Manag. Res., vol. 5, no. 2, 2020, doi: 10.29121/ijetmr.v5.i2.2018.633.

K. A. Wahid, M. A. Islam, S. S. Shimu, M. H. Lee, and S. B. Ko, “Hybrid architecture and VLSI implementation of the cosine-fourier-haar transforms,” Circuits, Syst. Signal Process., vol. 29, no. 6, 2010, doi: 10.1007/s00034-010-9200-x.

S. Das et al., “Transistors based on two-dimensional materials for future integrated circuits,” Nature Electronics, vol. 4, no. 11. 2021, doi: 10.1038/s41928-021-00670-1.

S. Bathla, N. Gaur, and A. Uniyal, “Power analysis of digital circuits for VLSI applications,” Int. J. Innov. Technol. Explor. Eng., vol. 8, no. 9 Special Issue, 2019, doi: 10.35940/ijitee.I1080.0789S19.

T. N. Phu Phu, D. P. Gia Han, N. C. Luong, and N. van Cuong, “Design a synchronous single-port sram 1024x32xMUX4 using 28NM technology,” Int. J. Comput. Digit. Syst., vol. 10, no. 1, 2021, doi: 10.12785/ijcds/100110.

R. Lorenzo and S. Chaudhury, “Review of Circuit Level Leakage Minimization Techniques in CMOS VLSI Circuits,” IETE Technical Review (Institution of Electronics and Telecommunication Engineers, India), vol. 34, no. 2. 2017, doi: 10.1080/02564602.2016.1162116.

“Improved Scheduling Algorithm for the IIR Filter design for Low power VLSI Applications,” Int. J. Adv. Trends Comput. Sci. Eng., vol. 9, no. 5, pp. 7461–7466, Oct. 2020, doi: 10.30534/ijatcse/2020/79952020.

“Adiabatic Logic Circuits for Low Power VLSI Applications,” Int. J. Sci. Res., vol. 5, no. 4, pp. 1585–1589, Apr. 2016, doi: 10.21275/v5i4.nov162225.

K. S. Chandra and K. H. Kishore, “Design Of Low Power Finfet Sram And Analysis Of Different Leakage Current Reduction Techniques,” ARPN J. Eng. Appl. Sci., vol. 16, no. 11, 2021.

R. Jegadeeswari, Ramyajothikumar, M. Mukila, and P. Raja, “Low-power and leakage reduction in 10t SRAM using tanner eda,” J. Crit. Rev., vol. 7, no. 8, 2020, doi: 10.31838/jcr.07.08.293.

A. B. Ch, J. V. R. Ravindra, and K. Lalkishore, “Design of Ultra-Low Power PMOS and NMOS for Nano Scale VLSI Circuits,” Circuits Syst., vol. 06, no. 03, 2015, doi: 10.4236/cs.2015.63007.

R. Islam and M. R. Guthaus, “CMCS: Current-Mode Clock Synthesis,” IEEE Trans. Very Large Scale Integr. Syst., vol. 25, no. 3, 2017, doi: 10.1109/TVLSI.2016.2605580.

Q. Zhou, Y. Cai, L. Huang, and X. Hong, “Incremental Placement-Based Clock Network Minimization Methodology,” Tsinghua Sci. Technol., vol. 13, no. 1, 2008, doi: 10.1016/S1007-0214(08)70013-0.

V. S. Chakravarthi, A Practical Approach to VLSI System on Chip (SoC) Design. 2020.

M. Ekandari and M. Yeganeh, “S-visibility problem in VLSI chip design,” Turkish J. Electr. Eng. Comput. Sci., vol. 25, no. 5, 2017, doi: 10.3906/elk-1608-281.

S. Wimer, “On optimal flip-flop grouping for VLSI power minimization,” Oper. Res. Lett., vol. 41, no. 5, 2013, doi: 10.1016/j.orl.2013.06.002.

S. Wimer, “Easy and difficult exact covering problems arising in VLSI power reduction by clock gating,” Discret. Optim., vol. 14, 2014, doi: 10.1016/j.disopt.2014.08.004.

A. Shetty, “ASIC Design Flow And Methodology – An Overview,” Int. J. Electr. Electron. Eng., vol. 6, no. 7, 2019, doi: 10.14445/23488379/ijeee-v6i7p101.

Y. Guo, T. Li, S. Li, D. Zhu, and L. Liang, “RT-Level verification framework - HRV,” Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal Comput. Des. Comput. Graph., vol. 16, no. 11, 2004.

S. Maheshwari, V. A. Bartlett, and I. Kale, “Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach,” Integration, vol. 67, 2019, doi: 10.1016/j.vlsi.2019.01.007.

M. Jayasanthi and A. K. Kowsalyadevi, “Low power implementation of linear feedback shift registers,” Int. J. Recent Technol. Eng., vol. 8, no. 2, 2019, doi: 10.35940/ijrte.A3379.078219.




DOI: https://doi.org/10.37628/jvdt.v7i2.1605

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