STUDY AND ANALYSIS LEAKAGE POWER REDUCTION TECHNIQUES FOR VLSI DESIGN

Abstract

The goal of low-power design is to reduce power to individual components as much as possible, thereby reducing overall power consumption. The power equation has components for dynamic and static power. Dynamic power includes switching and short-circuit power; Whereas static power involves leakage of current which flows through the transistor when there is no activity. With the rapid launch of battery powered applications, power dissipation has become one of the major concerns of VLSI circuit design. In high-performance designs, the leakage component of the power consumption is equal to the switching component. Unless effective techniques are introduced to bring the leak under control, this percentage will increase with the expansion of technology. The rapid growth of semiconductor technology and the growing demand for portable devices powered by batteries have prompted constructors to reduce feature sizes; This resulted in low threshold voltage as well as enabling the integration of incredibly complex functionality on a single chip. In both technical and implementation aspects, the chip's maximum power approach is adopted. To increase the concert of the equipment, three major factors are necessary such as system speed, small area and low power consumption. In particular, in integrated devices, the total power consumption is affected by the leakage current dissipation. There may be a demand for power leakage reduction.