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Novel Verilog Implementation of UART transmission with encryption and Single Error Correction
Abstract
Parallel and serial transmissions are both viable, but parallel transmission increases the cost and complexity of the system due to the simultaneous transmission of data bits over numerous cables. So we use serial transmission and Universal Asynchronous Receiver Transmitter is the most common and widely used device for serial transmission. In an industrial or military working environment employing multiprocessor communication using UART, noise may affect the data and because of that, we get the data with errors at the receiver side so authors use linear block code(LDC) to detect the errors and correct the errors. This type of logic detects faults and necessitates the retransmission of relevant data frames, which takes time due to the automatic repetition request (ARQ) and data retransmission. Linear block codes, such as hamming codes, can perform both forward error correction (FEC) and error detection. This work describes a revolutionary VLSI implementation of UART that includes a (7,4) extended Linear Block Code, also known as LBC code, that can rectify and detect up to two mistakes. This improves the system's noise immunity, allowing for error-free data reception. The complete design is implemented in Quartus and is targeted at the Xilinx Spartan 6 FPGA.
References
Naresh Patel, Vatsalkumar Patel, Vikaskumar Patel, ”VHDL Implementation of UART with Status Register”, 2012 IEEE International Conference on Communication Systems and Network Technologies, 2012.
S. Muppalla and K. R. Vaddempudi, ”A novel VHDL implementation of UART with single error correction and double error detection ca- pability,” 2015 International Conference on Signal Processing and Communication Engineering Systems, Guntur, India, 2015, pp. 152-156. doi: 10.1109/SPACES.2015.7058236
A. N. Borodzhieva, ”FPGA Implementation of Systematic Linear Block Encoders for Educational Purposes,” 2019 X National Conference with International Participation (ELECTRONICA), Sofia, Bulgaria, 2019, pp. 1-4. doi: 10.1109/ELECTRONICA.2019.8825652
G. Wiechman and I. Sason, ”Parity-Check Density Versus Performance of Binary Linear Block Codes: New Bounds and Applications,” in IEEE Transactions on Information Theory, vol. 53, no. 2, pp. 550-579, Feb. 2007. doi: 10.1109/TIT.2006.889606
R.W.Hamming, “Error detecting and error correcting codes”, The Bell System Technical journal Vol. XXIX, April 1950, Vol. 2, American Telephone and Telegraph company.
Elmenreich W, Delvai M, ”Time-triggered communication with UARTs”, 4thIEEE International Workshop on Factory Communication Systems, 2002, pp. 97- 104, 2002.
W. Lei, G. Yizhou, Z. Fucai and W. Yong, ”The Method to Recognize Linear Block Code Based on the Distribution of Code Weight,” 2018 10th International Conference on Communication Software and Networks (ICCSN), Chengdu, China, 2018, pp. 16-20.
G. Wiechman and I. Sason, ”Parity-Check Density Versus Performance of Binary Linear Block Codes: New Bounds and Applications,” in IEEE Transactions on Information Theory, vol. 53, no. 2, pp. 550-579, Feb. 2007. doi: 10.1109/TIT.2006.889606
T. Kasami, T. Klove and Shu Lin, ”Linear block codes for error detection (Corresp.),” in IEEE Transactions on Information Theory, vol. 29, no. 1, pp. 131-136, January 1983. doi: 10.1109/TIT.1983.1056615
Gallo R, Delvai M, Elmenreich W, Steininger A, “Revision and verification of an enhanced UART”, 2004, Proceedings, 2004 IEEE International Workshop on Factory Communication Systems, pp. 315- 318, 22-24, Sept. 2004.
Norhuzaimin J, Maimun H.H, ”The design of high speed UART”, AsiaPacific Conference on Applied Electromagnetics (APACE), pp. 20- 21, Dec. 2005.
A. K. Gupta, A. Raman, N. Kumar and R. Ranjan, ”Design and Implementation of High-Speed Universal Asynchronous Receiver and Trans- mitter (UART),” 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN), Noida, India, 2020, pp. 295-300. doi: 10.1109/SPIN48934.2020.9070856
T. Praveen Blessington, B. Bhanu Murthy, G. V. Ganesh and T. S. R. Prasad, ”Optimal implementation of UART-SPI Interface in SoC,” 2012 International Conference on Devices, Circuits and Systems (ICDCS), Coimbatore, India, 2012, pp. 673-677. doi: 10.1109/ICDCSyst.2012.6188657
Himanshu Patel, Sanjay Trivedi, R. Neelkanthan, V. R. Gujraty , ”A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance”, Held jointly with 6th International Conference on Embedded Systems, 20th International Conference on VLSI Design, pp. 819-823, Jan. 2007.
G. B. Wakhle, I. Aggarwal and S. Gaba, ”Synthesis and Implementation of UART Using VHDL Codes,” 2012 International Symposium on Computer,
Consumer and Control, Taichung, Taiwan, 2012, pp. 1-3. doi: 10.1109/IS3C.2012.10
U. Nanda and S. K. Pattnaik, ”Universal Asynchronous Receiver and Transmitter (UART),” 2016 3rd International Conference on Advanced Computing and Communication Systems (ICACCS), Coimbatore, India, 2016, pp. 1-5. doi: 10.1109/ICACCS.2016.7586376
L. Xie, D. Cai and G. Xu, ”Design of Serial Communication and Data Processing Platform Based on Visual Basic 6.0,” 2011 International Symposium on Computer Science and Society, Kota Kinabalu, Malaysia, 2011, pp. 240-243. doi: 10.1109/ISCCS.2011.72
M. J. Sarmah and S. Azeemuddin, ”A circuit to synchronize high speed serial communication channel,” 2014 International Conference on Field-
Programmable Technology (FPT), Shanghai, China, 2014, pp. 239-242. doi: 10.1109/FPT.2014.7082784
Fang Yi-yuan, Chen Xue-jun, ”Design and Simulation of UART Serial Communication Module Based on VHDL”, 2011 3rd International Workshop on Intelligent Systems and Applications (ISA), pp. 1-4, 28- 29, May 2011.
Y. -y. Fang and X. -j. Chen, ”Design and Simulation of UART Serial Communication Module Based on VHDL,” 2011 3rd International Workshop on Intelligent Systems and Applications, Wuhan, China, 2011, pp. 1-4. doi: 10.1109/ISA.2011.5873448
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