Open Access Open Access  Restricted Access Subscription or Fee Access

A systematic design approach of 5-bit digitally controlled attenuator using 130nm SiGe based BiCMOS technology for Ka –band applications

Shib sankar singh, M.Madhav Kumar, M.Madhav Kumar, Divya Kumar Garg, Divya Kumar Garg

Abstract


This paper present Ka-band 5-bit digital controlled attenuator with maximum attenuation   of 31.0 dB (32 states). The proposed attenuator has design using 130nm SiGe based BiCMOS technology. The proposed 5-bit digital controlled attenuator has design using simple approach. All the bits of attenuator have design using switch pi network topology to achieve the desired attenuation range, with low insertion loss and good input and output return loss. Traditionally pi attenuator design using two shunt arms with two individual grounds, but proposed attenuator used only one shunt arm grounding for reduce the size of layout. This is the novelty of design. This circuit achieved better than -10.0dB of input return loss over 32 states and -10.0dB of output return loss over 28 states and better than-9.5dB of output return loss in remaining 4 states at ka-band (35.5GHz-36.5GHz). This circuit achieved -7.678±0.2dB of insertion loss in reference state with less than +0.345dB of r.m.s. attenuation error at ka-band (35.5GHz-36.5GHz). With all including pad, the layout dimension of circuit is 1.289x0.404mm2.


Full Text:

PDF

References


Dogan. H.R.G. Meyer and A.M. Niknejad ” Analysis and Design of RF CMOS attenuator ”, IEEE Journal of Solid State Circuits vol.13 No.10, pp 2269-2283,2008

Hajimiri. A. “mm wave Silicon ICs; challenges and opportunities”, IEEE custom Integrated circuit conference, 2007

” A 37-40GHz Low-Phase Imbalance CMOS Attenuator with Tail-capacitor compensation Technique”Chenxi Zhao, Xing Zeng, Lin Zhang, Huihua Liu, Yiming Yu,Yunqiu Wu, Kai Kang, IEEE Transactions on Circuits and Systems, volume 67, October 2020

“6-bit Step Attenuators for Phased-Array System with Temperature Compensation Technique”,Ye Yuan, Shan-Xiang Mu, Yong-Xin Guo, IEEE Microwave and Wireless components Letters, vol.28, No.8 August 2018

J. Han, J. Kim, J. Park, and J. Kim, “A ka-band 4-ch bi-directional CMOS T/R chipset for 5G beamforming system,” inProc. IEEE RadioFreq. Integr. Circuits Symp. (RFIC), Honolulu, HI, USA, Jun. 2017,pp. 41–44

“A Novel Concurrent 22–29/57–64-GHz Dual-Band CMOS Step Attenuator With Low Phase Variations” Juseok Bae, Cam Nguyen, IEEE Transactions on Microwave Theory and Techniques, Vol. 64, No. 6, June 2016




DOI: https://doi.org/10.37628/jrfd.v7i2.1615

Refbacks

  • There are currently no refbacks.