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Low Power, High Reliability: A Survey of 10T SRAM Cells for Reduced Stand by Power and Enhanced Noise Resilience

K. Joseph Thanusha, Anusha Achhina, Deepya Yennamaneni

Abstract


With a focus on maximising power efficiency and attaining good read stability and write-ability, the project presents a low standby power 10T (LP10T) SRAM cell. The Schmitt-trigger inverter and the double-length pull-up transistor are combined with a regular inverter and stacked transistor to form a robust cross-coupled structure used in the LP10T SRAM cell. One of the key advantages of the LP10T SRAM cell is that it separates the read path from the true internal storage nodes, effectively eliminating read-disturbance issues. This division makes sure that the read operation doesn't tamper with the data that has been stored. In terms of write operation, the LP10T SRAM cell employs a pseudo-differential approach using a write bit line and control signal, supplemented by a write-assist technique. This arrangement improves the cell's write-ability. To evaluate the performance of the proposed LP10T SRAM cell, it is compared with several state-of-the-art SRAM cells using the Mentor Graphics tool in a 16-nm CMOS predictive technology model. The evaluation is conducted under harsh manufacturing process conditions, including variations in voltage and temperature, with a supply voltage of 0.8 V. The LP10T SRAM cell demonstrates favorable performance metrics compared to the other SRAM cells. It achieves the third-best read dynamic power and the second-best write dynamic power, with power reductions of 29.69% and 26.87%, respectively, when compared to the conventional 6T SRAM cell. Furthermore, the LP10T SRAM cell minimizes leakage power consumption through its design. It exhibits a leakage power reduction of 37.35% compared to the 6T SRAM cell and a 12.08% reduction compared to the best-studied cells. Overall, the proposed LP10T SRAM cell offers improved read stability and write-ability while significantly reducing power consumption, making it a promising choice for low-power and high-performance SRAM applications
 

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References


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