Open Access
Subscription or Fee Access
Efficient Implementation of the AES Using FPGA
Abstract
Rijndael encryption, developed by Joan Daemen and Vincent Rijmen and recently designated as the official Advanced Encryption Standard (AES), is well suited for hardware use.A few articles discuss the practical structures of ASIC and FPGA (FPGAs). This study proposes an effective way to integrate Rijndael encryption and encoding into a single FPGA architecture with minimal space constraints. The proposed project is equivalent to the smallest Xilinx FPGA, manages 208 Mbps data transmission, uses 163 pieces and three blocks of RAM, and exceeds similarly well-known designs by 68 percent according to the Phryput / Area rating. This paper also includes coarisons with other FPGA families' DES, tripleDES, and AES implementations (such as the Xilinx Virtex-II).
References
J. Daemen and V. Rijmen. The Block Cipher RIJNDAEL, NIST's AES home page[online],
available from http://www.nist.gov/aes.
National Bureau of Standards. FIPS PUB 46, The Data Encryption Standard. U.S. Departement of
Commerce, Jan 1977.
Xilinx. The Virtex-II field programmable gate arrays data sheet, available [online] Available From
http://www.xilinx.com.
K. Gaj and P. Chodowiec. Very Compact FPGA Implementation of the AES Algorithm. In the
proceedings of CHES 2003, Lecture Notes in Computer Science, vol 2779, pp. 319–333,
P. Chodowiec, K. Gaj, P. Bellows and B. Schott. Experimental Testing of the Gigabit IPSecCompliant Implementations of RIJNDAEL and Triple DES Using SLAAC-1V FPGA Accelerator
International Journal of Digital Communication and Analog Signals
Volume 7, Issue 1
ISSN: 2455-0329
© JournalsPub 2021. All Rights Reserved 26
Board. In Proc. Of ISC 2001: Information Security Workshop, LNCS 2200, Pp.220–234
G. Rouvroy, FX. Standaert, JJ. Quisquater, JD. Legat. Design Strategies And Modi_ed Descriptions
to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and TripleDES. In
the proceedings of FPL 2003, Lecture Notes in Computer Science, vol 2778, pp. 181–193
V. Fischer and M. Drutarovsky. Two Methods of RIJNDAEL Implementation in Recon_gurable
Hardware. In the proceedings of CHES 2001: The Third International CHES Workshop, Lecture
Notes In Computer Science, LNCS2162, pp 65–76.
A. Rudra et al. Ef_cient RIJNDAEL Encryption Implementation with Composite Field Arithmetic.
In the proceedings of CHES 2001: The Third International CHES Workshop, Lecture Notes In
Computer Science, LNCS2162, pp 65–76
A.J. Elbert, E. Yip, B. Chetwynd, C. Paar: An FPGA Implementation and Performance Evaluation
of the AES Block Cipher Candidate Algorithm Finalists, IEEE Transactions on VLSI, August 2001,
vol. 9, no. 4, pp. 545–557.
M. McLoone, J.V McCanny: High Performance Single-Chip FPGA Rijndael Algorithm
Implementations, CHES 2001, pp. 65–76.
Xilinx VirtexTM-E 1.8V Field Programmable Gate Arrays: URL: http://www.xilinx.com:
November 2000.
P.Baretto, V.Rijmen, The khazad Legacy-Level Block Cipher, Submission to NESSIE project,
available from http://www.cosic.esat.kuleuven.ac.be/nessie/
S. Trimberger, R. Pang and A. Singh. A 12 Gbps DES encryptor/ decryptor core in an FPGA. In
Proc. of CHES'00, LNCS, Pp 156.163.
Xilinx, V. Pasham and S. Trimberger. High-Speed DES and Triple DES Encryptor/Decryptor.
[online] available from http://www.xilinx.com/xapp/xapp270.
M. McLoone and J.V. McCanny, Single-Chip FPGA Implementation of the Advanced Encryption
Standard Algorithm. In the proceedings of FPL 2002: The Field Programmable Logic Conference,
Lecture Notes in Computer Science, LNCS 2147, p.152ff.
K.U. Jarvinen, M.T. Tommiska and J.O. Skytta A fully Pipelined Memoryless 17.8 Gbps AES-128
Encryptor. In the proceedings of FPGA 2003: Symposium on Field-Programmable Gate Arrays,
pp. 207–215
N. Weaver and J. Wawrzynek. High Performance Compact AES Implementations in Xilinx FPGA
[online] available from http://www.cs.berkeley.edu/ nweaver/Rijndael.8
Refbacks
- There are currently no refbacks.