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Comparison of Different Full Adders and its Applications

Cilveri Praneeth Kumar, Choragudi Krishna Chaitanya, Malyala Sai Siddeshwar, G. R. Padmini

Abstract


Full Adder is a fundamental block in Arithmetic and Logical unit (ALU) which is a core of any processor. It is extensively used in General Purpose Processors (GPP) along with various Application Specific Processors (ASP) like Digital Signal Processor (DSP) for addition, subtraction, multiplication and counting operations. Reducing the power of most repetitively used block in a circuit reduces the overall power of the circuit. Adopting Low Power techniques ensures Power Efficient Full Adder. The prominent approaches include reducing the transistor count which is strategically reducing the size and power of the chip. Furthermore, reducing the activity factor, Dual VDD method, circuit parallelization, Clock gating are practices that reduces the power of any VLSI circuit. Comparisons are made by verifying 28 transistor Complementary Metal Oxide Semiconductor (CMOS) technology, 14 transistors and 10 transistors 1-bit full adders using Cadence virtuoso generic process design kit 45 45 nm (gpdk045) technology. This power efficient full adder is utilized for designing power efficient N-bit adders, subsequently the trends in power are analysed with N-bit CMOS full adder.


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References


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