Open Access
Subscription or Fee Access
Design and Simulation of Directory-based Cache Coherence Protocols using Verilog
Abstract
A cache coherence mechanism ensures the system's data consistency. Modern microprocessors are typically built with a multicore architecture, which requires data transfers from one cache to another. The coherency problem can be solved by applying cache coherence protocols to each of the caches. Simulations of the applicable cache coherence procedures can each be given with this resolution to walk-through the coherency processes. The read and write operations of the cache are included in the cache coherence protocols.
For networked shared memory systems, we create a family of cache coherence protocols. Each protocol is tailored to certain access patterns and includes a set of optional rules for adaptivity that can be used as needed. Cachet is an adaptive cache coherence mechanism that enables huge adaptivity for programmes with various access patterns. The Cachet protocol incorporates both intra-protocol and inter-protocol adaptivity, which can be utilized via proper heuristic techniques to obtain optical performances.
Cache coherence methods are used to preserve data consistency between cache memories in centralized and remote shared-memory multiprocessor systems. The type of cache coherence protocol utilized has a significant impact on the performance of a multi-core computer system. In this paper, a basic implementation of directory-based cache coherence protocol is implemented using Verilog.
References
Chaiken D, Fields C, Kurihara K, Agarwal A. Directory-based cache coherence in large-scale multiprocessors. Computer. 1990 Jun;23(6):49-58.
Jang YJ, Ro WW. Evaluation of cache coherence protocols on multi-core systems with linear workloads. In2009 ISECS International Colloquium on Computing, Communication, Control, and Management 2009 Aug 8 (Vol. 4, pp. 342-345). IEEE.
Joshi AD, Indrajeet S, Ramasubramanian N, Begum BS. Analysis of multi-core cache coherence protocols from energy and performance perspective. In2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE) 2017 Oct 27 (pp. 381-388). IEEE.
Kaur DP, Sulochana V. Design and implementation of cache coherence protocol for high-speed multiprocessor system. In2018 2nd IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES) 2018 Oct 22 (pp. 1097-1102). IEEE.
Baer, J.-L. and Chen, T.-F., “An Effective On-chip Preloading Scheme toReduce Data Access Penalty,” in Supercomputing ’91, 1991.
Baghdadi, A., Lyonnard, D., Zergainoh, N., and Jerraya, A., “An Efficient Architecture Model for Systematic Design of Application-Specific Multiprocessor SoC,” in Proceedings of the Design Automation and Test in Europe (DATE), pp. 55–63, 2001.
Bailey, D. H., Barszcz, E., Barton, J. T., Browning, D. S., Carter, R. L., Dagum, D., Fatoohi, R. A., Frederickson, P. O., Lasinski, T. A., Schreiber, R. S., Simon, H. D., Venkatakrishnan, V., and Weeratunga, S. K., “The NAS Parallel Benchmarks,” The International Journal of Supercomputer Applications, vol. 5, no. 3, pp. 63–73, 1991.
Barroso, L. A., Gharachorloo, K., McNamara, R., Nowatzyk, A., Qadeer, S., Sano, B., Smith, S., Stets, R., and Verghese, B., “Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing,” in Proceedings of the 22nd Annual International Symposium on Computer Architecture, pp. 282–293, 2000.
Baskett, F., Jermoluk, T., and Solomon, D., “The 4D-MP Graphics Superworkstation: Computing + Graphics = 40 MIPS + 40 MFLOPS and 100,000 Lighted Polygons per Second,” in Proceedings of the 33rd IEEE Computer Society International Conference - COMPCON 88, pp. 468–471, Feb. 1988.
Bechini, A., Foglia, P., and Prete, C. A., “Fine-Grain Design Space Exploration for a Cartographic SoC Multiprocessor,” ACM SigArch Computer Architecture News, vol. 31, no. 1, pp. 85–92, 2003.
Refbacks
- There are currently no refbacks.