Development of Verification Environment for Universal Memory Controller

Abstract

Increasing the performance of memory is important for increasing computer performance. With the use of a memory controller, data may be transferred between the processor and memory more effectively. Memory controllers have the main purpose of creating a high speed, secure, dataintegrity,
and information-retention interface between a host and a memory. Without memory controller the processor design will get very complex. In enhancing memory controller performance, a large amount of effort, resources, and time are consumed by the verification process. Verification in
the pre-silicon stage is considered an important concern to avoid chip defects due to design errors,specification errors. Developing the verification environment is a difficult task due to the difficulty in building and reusing resources, the number of protocols the verifier must understand, and the high number of iterations needed to attain full functional coverage. To verify universal memory controllers (UMC), this paper presents an optimized generic verification environment. The UMC used for the verification supports Static Random Access Memory (SRAM), Synchronous Dynamic Random Access Memory (SDRAM), FLASH memory, and Synchronous Chip Select Device (SCSD) memory with an open-source wishbone (WB) interface. This memory controller has many special features which make verification more difficult. A proposed verification methodology is configurable, scalable, reusable, and reduces the time it takes for verification to be completed. The proposed test plan verifies all the features of UMC provided in the specification sheet, and the regression test shows 100% coverage.
The proposed verification methodology has good portability and improves verification efficiency. It meets the requirements for chip validation.