Implementation of Kogge–Stone Adder Using Binary Logic with Low Power and High Speed
DOI:
https://doi.org/10.37628/jvdt.v4i1.764Abstract
Low-energy and low-voltage circuits are important for many reasons. Propagation delay on portable devices adds to the mobility and utility of the device. As the growing complexity of mobile electronics applications leads to prohibitively high chip power demands, the energy efficiency of the integrated circuit devices will become more significant. Reduced propagation delay circuitry based on binary logic complementary metal-oxide-semiconductor (CMOS) principles is a relatively new technique used to implement low-energy-dissipating circuits. The goal of this work was to develop a reduced propagation delay circuitry based on binary CMOS technology. The binary-based circuit has been designed for low-voltage, low-energy, high-speed operation. A layout-based simulation was then performed to verify the operation. Simulations demonstrate that the new logic family is suitable for low-voltage operation down to the 90-nm CMOS technology. Here the circuits implemented are half adder, full adder by using binary AND, NAND, OR, NOR, EXOR, EXNOR logic gates, and parallel-prefix hybrid adders (Kogge–Stone).References
Das S, Khatri SP. A novel hybrid parallel- prefix adder architecture with efficient timing-area characterstic. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2008; 16(3): 326–331p.
Lm YC, Su CY. Faster optimal parallel prefix circuit: new algorithm construction. J Parall Distrib Comput. 2005; 65(12): 1585–1595p.
Choi Y, Swatzlandr Jr. EE. Parallel prefix adder design with matrix representation. In: Proceedings of17th IEEE Symposium Computer Arithmetic, Cape Cod, MA, USA. 2005, pp. 90–98.
Brent RP, Kung HT. A regular layout for parallel adders. IEEE Trans Comput. 1982; 31(3): 260–264p.
Ladner RE, Fischer MI. Parallel prefix computation. J ACM. 1980; 27(4): 831–838p.
Knowles S. A family of adders. In: Proceedings of 14th IEEE Symposium on Computer Arithmetic, Adelaide, Australia. 1999, April 14–16, pp. 30–34.
Dimitrakopoulos G, Nikolas D. High speed parallel prefix VLSI ling adders. IEEE Trans Comput. 2005; 54(2).
Kogge PM, Stone HS. A parallel algorithm for the efficient solution of a general class of recurrence equations. IEEE Trans Comput. 1973; C-22(8): 783–791p.
