Optimizing Switching Power With Advanced Clock Gating Approach in Low Power VLSI Design
DOI:
https://doi.org/10.37628/jvdt.v3i1.591Abstract
Clock gating is a technique which is used for reducing dynamic power in sequential circuits. Power is saved by dividing the clock and then distributing the clock to the logic blocks only when there is a need for those blocks to be activated. In this paper, we have optimized dynamic power on ROM using different FPGA families namely Spartan-6, Virtex-7, Artix-7 and Kintex-7 in X-Power Analyzer in both ways i.e. with clock gating and without clock gating technique. So, in this way we have demonstrated the power reduction by using clock gating technique. The whole design is implemented in VHDL and mapped onto Xilinx 14.7.References
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