High speed low power analysis of mixed logic line decoder using 45GPDK Technology.
DOI:
https://doi.org/10.37628/ijaic.v9i2.1949Abstract
A huge challenge faced by this era of development is power reduction. The low power circuit designs are a requesting issue in high performance digital frameworks, for example, microchips, DSPs, and other different applications. Power and speed are the main highlights considered when comparing any circuit or design. The diminishing chip area is additionally truly impressive factor, creators need to recall when suggesting any novel design. 2×4 Decoder Using 12 T is used for conversion of binary inputs to associate output bits in a pattern. A novel 2:4 decoder Using 12T is proposed with area optimization in this paper. CMOS logic is additionally used for execution of 2:4 decoder. Delay and power are used for evaluation between the novel design and CMOS logic. The novel design of 2:4 decoder is 60.72% optimized for power in contrast to CMOS logic design at a typical value of 1.8V. The proposed method has been validated using Cadence 45GPDK (Generic Product Design Key) Virtuoso Tool
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