Design and Simulation of Low Power CMOS Half Adder

Authors

  • Jyoti Gahlawat Ganga Institute of Technology and Management, Kablana, Haryana

Abstract

This experiment presents the design and simulation of low power complementary metal oxide semiconductor (CMOS) half adder. This paper gives an idea to reduce power of half adder circuit. An adder is basically a digital circuit that performs addition of two numbers. In several computers and also in other kind of processors, adders are not only used in arithmetic logic unit but also in they are used in other parts of the processors to calculate addresses, table indices and similar operations. For simulation purpose LT SPICE is used. According to simulation result power is reduced.

Author Biography

  • Jyoti Gahlawat, Ganga Institute of Technology and Management, Kablana, Haryana
    Department of Electronics and Communication Engineering

References

P. Verma. Design of area and power efficient half adder using transmission gate, Int J Res Eng Technol.

J. Praveen. Design and simulation of low power CMOS ternary Full Adder, Int J Res. 2017; 4(14).

S. Baghel. CMOS Half Adder design and simulation using different foundary, Int J Innov Sci Eng Technol. 2015; 2(3).

A.K. Singh. Design and simulation of half adder circuit using AVL technique based on CMOS technology, Int Res J Eng Technol. 2017; 4(8).

Mahesh. Design of low power half adder using adaptive voltage level (AVL) technique, Int J Adv Res Electr Electron Instrum Eng. 2015; 4(4).

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Published

2022-11-07

Issue

Vol. 3 No. 2 (2017)

Section

Articles