Implementation of Kogge–Stone Adder Using Binary Logic with Low Power and High Speed

Abstract

Low-energy and low-voltage circuits are important for many reasons. Propagation delay on portable devices adds to the mobility and utility of the device. As the growing complexity of mobile electronics applications leads to prohibitively high chip power demands, the energy efficiency of the integrated circuit devices will become more significant. Reduced propagation delay circuitry based on binary logic complementary metal-oxide-semiconductor (CMOS) principles is a relatively new technique used to implement low-energy-dissipating circuits. The goal of this work was to develop a reduced propagation delay circuitry based on binary CMOS technology. The binary-based circuit has been designed for low-voltage, low-energy, high-speed operation. A layout-based simulation was then performed to verify the operation. Simulations demonstrate that the new logic family is suitable for low-voltage operation down to the 90-nm CMOS technology. Here the circuits implemented are half adder, full adder by using binary AND, NAND, OR, NOR, EXOR, EXNOR logic gates, and parallel-prefix hybrid adders (Kogge–Stone).