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Comparision of Adders for High Speed ALU

Arun Dev Dhar Dwiwedi, Rohit Kumar Bairwa, Chanchal Soni, Roopendra Kumar, Deepak Kumar

Abstract


In this paper, logic optimized multiplexer based adders are incorporated in selected existing adders like ripple carry adder, carry look-ahead adder, carry skip adder, carry select adder, and carry save adder and its performance is analyzed in terms of area (slices used) and maximum combinational path delay as a function of size. Here, different adder architectures are simulated and analyzed based on power dissipation, area and speed by using Xilinx 14.4 ISE simulator and Verilog HDL. Hence, with the fast developments in the VLSI technology and design, it is extremely important to include the interconnect sub circuitry during the simulation process as efficiently as possible.

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