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Comparative study of a 32 Bit Vedic Multiplier with a Conventional Binary Multiplier

Rohan Muley, Amrita Tuteja

Abstract


Multiplier plays a very important role in digital signal processing systems. To achieve high speed operation, Vedic method has been adopted in VLSI technology. Multipliers using vedic mathematics produces high evaluation results in terms of speed and device utilization. The aim of this work is to design digital multipliers based on the idea of Vedic mathematics. In order to implement a digital multiplier, Urdhva-tiryakbyham sutras of Vedic mathematics are used to develop vertical and cross wise operations. After all these are digital multiplier, so that they are implemented on FPGA board and tested through the 8 LED (s) in FPGA (Nexys 3). An implemented 32-bit Vedic multiplier has been simulated in Xilinx ISE 13.4 and compared with a 32-bit binary multiplier.

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References


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