Comparative study of a 32 Bit Vedic Multiplier with a Conventional Binary Multiplier
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Wallace, C.S., “A suggestion for a fast multiplier,” IEEE Trans. Elec. Comput., vol. EC-13, no. 1, pp. 14–17, Feb. 1964.
H.D. Tiwari, G. Gankhuyag, Chan-Mo Kim, Yong Beom Cho, "Multiplier design based on ancient Indian Vedic Mathematics", International SoC Design Conference, Vol. 2, pp. 65-68, Nov 2008 doi: 10.1 I 09fSOCDC.2008.48 I 5685
S. Akhter, "VHDL implementation of fast NxN multiplier based on Vedic
mathematic", 18th European Conference on Circuit Theory and Design, pp.
-475, Aug 2007
doi: 10. I 109fECCTD.2007.4529635
H.D. Tiwari, G. Gankhuyag, Chan-Mo Kim, Yong Beom Cho, "Multiplier design based on ancient Indian Vedic Mathematics", International SoC Design Conference, Vol. 2, pp. 65-68, Nov 2008 doi: 10.1 I 09fSOCDC.2008.48 I 5685
P. Mehta and D. Gawali, "Conventional versus Vedic Mathematical Method for Hardware Implementation of a Multiplier", International Conference on Advances in Computing, Control & Telecommunication Technologies, pp. 640-642, Dec 2009 doi: 10.1l09fACT.2009.162
P. Saha, A Banerjee, P. Bhattacharyya, A Dandapat, "High speed ASIC design of complex multiplier using Vedic Mathematics", IEEE Students' Technology Symposium , pp. 237-241, Jan 2011 doi: 10.1109fTECHSYM.2011.5783852
D. Jaina, K. Sethi, R. Panda, "Vedic Mathematics Based Multiply Accumulate Unit", International Conference on Computational Intelligence and Communication Networks, pp. 754-757, Oct 2011 doi: 10.1l09fCICN.2011.167
J.M. Rudagi, Vishwanath Ambli, Vishwanath Munavalli, Ravindra Patil, Vinaykumar Sajjan, "Design and implementation of efficient multiplier using Vedic Mathematics", 3rd International Conference on Advances in Recent Technologies in Communication and Computing, pp. 162-166, Nov 2011 doi: 10.1 049fic.20 11.0071
A Haveliya, "FPGA implementation of a Vedic convolution algorithm", International journal of engineering research and applications, Vol. 2, issue I, pp. 678-684, Feb 2012
AK. ltawadiya, R. Mahle, and V. Patel, D. Kumar, "Design a DSP operations using Vedic mathematics", International Conference on Communications and Signal Processing, pp. 897-902, Apr 2013 doi: 10.1109ficcsp.2013.6577186
L. Srirarnan, K. Kumar, T.N. Saravana, Prabakar, "Design and FPGA implementation of binary squarer using Vedic mathematics", Fourth International Conference on Computing, Communications and Networking Technologies, pp. 1-5, July 2013 doi: 10.11 09f1CCCNT.20 13.6726607 1760
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