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ENERGY EFFICIENT LOW-VOLTAGE DYNAMIC COMPARATOR

Sushil Kumar Jain, C Periasamy

Abstract


The blueprint of a comparator that is doubly tailed & with minimal voltage post amplifier & stage of latching are explained deeply in this document. The main concern of the design is in the comparator of traditional modes those are doubly tailed. The circuitry which is traditionally doubly tailed is manipulated as per the need of minimal power & enhanced operation in voltages with very minutes supply. In the technique of CMOS of 45 nm the outcomes of simulation ensures the outcomes of assessments. It is also presented that by minimizing the extent of channel, the absorption of power will also be deduced. The voltage of 1.2v that is furnished is absorbed as 4.11μw in the comparator suggested here while it is 39.05μw & 136.55μw in the comparators those are currently in use.

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References


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DOI: https://doi.org/10.37628/jvdt.v2i2.317

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