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Comparative Analysis of Multi- Synchronous Bidirectional Network-on-Chip Architecture

Bharati Sayankar, Pankaj Rangaree

Abstract


ABSTRACT

A dynamic reconfigurable multi-synchronous bidirectional channel network on chip architecture is proposed to improve the performance of on chip communication. This work aims to increase network-on-chip (NOC) in the runtime traffic situation. The main objective of this paper is to reduce the area, delay and power consumption of the architecture. Lower packet delivery latency, higher packet consumption rate and better bandwidth utilization is done by the multi-synchronous bidirectional NoC’s router. The design is implemented in VHDL and simulated in Xilinx ISE design suite and performance is evaluated in terms of power, area, and delay.

 

Keywords: Network-on-chip, Router, virtual-cut-through switching, crossbar switch, arbiter; On-chip communications.

Cite this Article: Bharati Sayankar, Pankaj Rangaree. Comparative Analysis of Multi- Synchronous Bidirectional Network-on-Chip Architecture. International Journal of Telecommunications & Emerging Technologies. 2019; 5(2): 21–31p.


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References


Faizal A. Samman, Thomas Hollstein, Manfred Glesner: “Multicast Parallel Pipeline Router Architecture for Network on-Chip” Published In 2008 Design, Automation and Test in Europe, ISBN: 978-3-9810801-3-1 978-3-9810801-3-1/DATE08 2008 EDAA. Munich, Germany — March 10–14, 2008

Y.C. Lan, H.A. Lin, S.H. Lo, Y.H. Hu, S.J. Chen, A Bidirectional NoC (BiNoC) architecture with dynamic selfreconfigurable channel, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (Volume: 30, Issue: 3, March 2011) PP 427–440.

M.H. Cho, M. Lis, M. Kinsy, K.S. Shim, T. Wen, S. Devadas, Oblivious routing in on-chip bandwidth-adaptive networks, in: Proc. PACT, 2009, pp. 181– 190. Electronic Design Automation, vol. 13, no. 1–2, pp. 1–144, 2019.ISBN: 978-1-68083-579-3

M.A.A. Faruque, T. Ebi, J. Henkel, “Configurable links for runtime adaptive on-chip communication”, 2009 Design, Automation & Test in Europe Conference & Exhibition, 20–24 April 2009, Nice, France.

Zhu, Z. Qian, C.Y. Tsui, BiLink: A high performance NoC router architecture using bidirectional link with double data rate, Integration. The VLSI Journal,v 55 (2016),PP 30–42.

Evangelia Kasapaki, Martin Schoeberl, Rasmus Bo Sørensen, Christoph Müller, Kees Goossens, Jens Sparsø: Argo:A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 24, no. 2,PP 479–492, february 2016.

R. Kumar, H. Deshpande, G. Choi, A. Sprintson, P. Gratz: Bidirectional Interconnect Design for Low Latency High Bandwidth NoC, Proceedings of 2013 International Conference on IC Design & Technology (ICICDT), ICICDT 2013, Pavia, Italy, 978-1-4673 4743-3/13/$31.00 ©2013 IEEE,.

Fakhrali S, Zarandi H R. Double Stairs, “A Fault-Tolerant Routing Algorithm for Networks-on-Chip”. Journal of Circuits System & Computers, 2016, V25(6), pp.

(2016), 10.1142/S0218126616500651.

Somasundaram K, Plosila J. Deadlock Free Routing Algorithm for Minimizing Data Packet Transmission in Network on Chip. International Journal of Embedded and Real-Time Communication Systems, 2012, 3(1), pp.70–81.

Hu S, Xu W, Lin J, et al. Probabilistic odd–even, an adaptive wormhole routing algorithm for 2D mesh network-on-chip. The Journal of Supercomputing, 2014, 70(1), pp.385-407.

Umamaheswari S, Meganathan D, Raja P P J. Runtime buffer management to improve the performance in irregular Network-on-Chip architecture. Sādhanā, Springer 2015, 40(4), pp. 1117–1137.

Nam-Khanh Dang, Thanh-Vu Le-Van, Xuan-Tu Tran, “FPGA Implementation of a Low Latency and High Throughput Network-on-Chip Router Architecture,” The Institute of Electronics, Information and Communication Engineers, IEICE ICDV 2011.




DOI: https://doi.org/10.37628/ijtet.v5i2.1195

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