High Performance 64-Bit Vedic MAC with Logic BIST Features

Abstract

Multiply and Accumulate (MAC) is a very important operation in most of the DSP applications such as FIR/IIR filters, convolutions, and FFT computations. Therefore, every DSP processor will incorporate a hardware MAC for high-performance operations. However, most of the MAC architectures do not have self-testing features. It is very essential to embed self-testing features in the MAC design for accurate and reliable operation thus avoiding the need for expensive external testing. This paper presents the implementation of a 64-Bit high-performance Vedic MAC embedded with testability features such as Logic Built-In Self-Test (LBIST) and Automatic Test Pattern Generator (ATPG). As part of LBIST, a static fault model is implemented to obtain maximum fault coverage. The 64-Bit MAC is implemented using a fast Vedic Multiplier and a fast adder (Carry Look Ahead Adder) with a pipeline mechanism to achieve high-performance. The design is implemented in 90nm Technology using Cadence tools. Typical results show that the 64-Bit Vedic MAC operates at 100MHz with a static fault coverage of 99.43%.