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Design and Simulation of Low Power CMOS Half Adder

Jyoti Gahlawat

Abstract


This experiment presents the design and simulation of low power complementary metal oxide semiconductor (CMOS) half adder. This paper gives an idea to reduce power of half adder circuit. An adder is basically a digital circuit that performs addition of two numbers. In several computers and also in other kind of processors, adders are not only used in arithmetic logic unit but also in they are used in other parts of the processors to calculate addresses, table indices and similar operations. For simulation purpose LT SPICE is used. According to simulation result power is reduced.

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References


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