1 Bit Full Adder Design using 14 Transistors Using Novel 3 Transistors XOR Gate
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Y. Leblebici and S.M. Kang, CMOS Digital Digital Integrated Circuits,
Singapore: McGraw Hill, India, 2nd edition, 1999.
R. Zimmermann and W. Fichtner, “Low-power logic styles: CMOS versus pass-transistor logic,” IEEE J. Solid State Circuits, vol. 32, no. 7, pp. 1079-1090, Jul. 1997.
N. Weste and K. Eshraghian, Principles of CMOS VLSI Design,A System Perspective, Addison-Wesley, 1993.
N. Zhuang and H. Wu, “A new design of the CMOS full adder,” IEEE J.Solid-State Circuits, vol. 27, no. 5, pp. 840–844, May 1992.
Yingtao Jiang, Abdulkarim Al-Sheraidah, Yuke Wang, Edwin Sha, and Jin-Gyun Chung, “A novel multiplexer-based low-power full adder,”
IEEE Transactions on Circuits and Systems: Express Briefs, vol. 51, no.7, Jul. 2004.
R. Shalem, E. John, and L. K. John, “A novel low-power energy recovery full adder cell,” in Proc. of Great Lakes Symp. VLSI, Feb. 1999, pp. 380– 383.
H. T. Bui, Y. Wang, and Y. Jiang, “Design and analysis of low-power 10-transistor full adders using XOR-XNOR gates,” IEEE Trans. CircuitsSyst. II, Analog Digit. Signal Process, vol. 49, no. 1, pp. 25– 30, Jan.2002.
S. Goel,A. Kumar, and M. A. Bayoumi, “Design of robust, energy– efficient full adders for deep sub micrometer design using hybrid-CMOS logic style,” IEEE Transactions on Very Large Scale Integration (VLSI)Systems, vol.14, no.12, pp.1309-1321, Dec. 2006.
M. Zhang, J. Gu, and C. H. Chang, “A novel hybrid pass logic with static CMOS output drive full-adder cell,” Proc. IEEE Int. Symp. Circuits Syst.,
May 2003, pp. 317-32.
C. K. Tung, Y. C. Hung, S. H. Shieh, and G. S. Huang, “ A low-power high-speed hybrid CMOS full adder for embedded system,” IEEE conf.on Design and Diagnostics of Electronic Circuits and Systems, 2007,pp.1-4.
A. M. Shams and M. Bayoumi, “A novel high- erformance CMOS1-bit full adder cell,” IEEE Trans. Circuits Syst. II, Analog Digital SignalProcess, vol. 47, no. 5, pp. 478–481, May 2000.
A. M. Shams and A. Magdy, “A structured approach for designing low power adders,” Conference Record of the Thirty-First AsilomarConference on Signals, Systems & Computers, Nov. 1997, vol. 1, pp.757-761.
D. Radhakrishnan, “Low-voltage low-power CMOS full adder,” Proc.IEE Circuits Devices Syst., Feb. 2001, vol. 148, pp. 19-24.
J. M. Wang, S. C. Fang, and W. S. Feng, “New efficient designs for XOR and XNOR functions on the transistor level,” IEEE J. Solid-State Circuits, vol. 29, no. 7, pp. 780–786, Jul. 1994.
H. T. Bui, A. K. Al Sheraidah, and Y.Wang, “New 4-transistor XOR and XNOR designs,” in Proc. 2nd IEEE Asia Pacific Conf. ASIC, 2000, pp. 25–28.
H. T. Bui, Y. Wang, and Y. Jiang , “Design and analysis of 10-transistor full adders using novel XOR–XNOR gates,” in Proc. 5thInt. Conf. SignalProcess, Aug. 21–25, 2000, vol. 1, pp. 619–622.
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