http://ecc.journalspub.info/index.php/JVDT/issue/feedInternational Journal of VLSI Design and Technology2017-08-25T05:24:56-07:00Editor in Chiefinfo@journalspub.comOpen Journal SystemsJournals aim is to cover all aspects of VLSI technologies and their integration into recent technologies that are the focus of ongoing research. Journal has a wider scope including all major advancement in the technology and design that are related to VLSI. All articles presented here are peer-reviewed and are of good quality.http://ecc.journalspub.info/index.php/JVDT/article/view/417TWO NOVEL APPLICATIONS OF SPICE2017-08-25T05:24:55-07:00Krishnapuram Kumarbbkrishnapuram3@yahoo.comTwo novel applications of SPICE in the area of (i) two circuit theorems’ parameter determination and (ii) voltage/current dependent sources’ delay time are given. In the first case, applications of SPICE in obtaining Thevenin/ Norton’s equivalent circuit voltage/current and immittances are demonstrated. A SPICE file which prints all the four Thevenin/Norton parameters simultaneously is described. In the second application, the time delays in the dependent sources ( which are used in simulating small signal equivalent circuits for high frequency devices (Bipolar, HEMT) used in time and frequency domains) are realized by suitable SPICE compatible techniques. Simulation results in the frequency domain incorporating these delays for two types of devices are plotted.2017-05-17T23:39:48-07:00http://ecc.journalspub.info/index.php/JVDT/article/view/540Stability Control of Transient Response of Four-Leg Voltage Source Inverter2017-08-25T05:24:56-07:00AMUTHA PRIYAa.amazing13@gmail.comN Anujaa.amazing13@gmail.comFour-leg voltage source inverters require a balanced sinusoidal output voltage for supplying unbalanced and/or nonlinear loads. Four-leg voltage source inverters are more advantageous than 3-leg voltage source inverters in such a way by the greater utilization of DC link voltage, independency of the modulation factor of load current and avoidance of superposition of a DC component with the AC output voltage. Pole Placement Control technique via state feedback is used to achieve an accurate adjustment of the transient performance of the inverter and to track its reference input under steady state conditions. Its transient performance is compared with that of Ziegler-Nichols’ tuned proportional-integral and proportional-integral-derivative controllers and linear quadratic regulator. Also, adaptive pole placement control technique is utilized to make the inverter to adapt to the changes when load variation occurs in the system.2017-08-05T04:34:52-07:00http://ecc.journalspub.info/index.php/JVDT/article/view/582SPICE2G for Two Port Z Parameter Simulation of Circuits2017-08-25T05:24:56-07:00Krishnapuram Kumarbbkrishnapuram3@yahoo.comFrom the definition of Z parameters, models for simulating various electronic SPICE circuits having two port networks are developed. The procedure and technique for simulation of two ports using Y, G, H, transmission and inverse transmission parameters can be extended by similar steps as is done to the Z parameters for a two port.2017-08-24T04:00:36-07:00http://ecc.journalspub.info/index.php/JVDT/article/view/583Z,Y,H,G, and S Parameters for Circuits Using Spice2017-08-25T05:24:56-07:00Krishnapuram Kumarbbkrishnapuram3@yahoo.comSpice compatible circuit files and procedures for linear two port Z,Y,G,H and S parameters are given. Starting from definitions of two port parameters the various parameters are determined for a fictitious circuit. For the same parameter determination one or more than one change in spice netlist statements are indicated. Three different files for the determination of S parameters is given. The thoery behind the written netlist is explained. Different input spice files for Z,Y,G,H parameters using independent voltage sources, resistors, dependent current/voltage sources, independent current sources with spice compatible procedures are given. The Z,Y,G,H parameter output for a typical file are generated and given in the form of tables and graph. Analog behavioral option of pspice is also used for two of the four files to calculate all the four S11,S12,S21 and S22.2017-08-24T04:55:46-07:00http://ecc.journalspub.info/index.php/JVDT/article/view/591Optimizing Switching Power With Advanced Clock Gating Approach in Low Power VLSI Design2017-08-25T05:24:56-07:00Akash Singhakash0076@gmail.comAnjan Kumarakash0076@gmail.comAnkit Agrawalakash0076@gmail.comAman Goswamiakash0076@gmail.comShivam Dubeyakash0076@gmail.comClock gating is a technique which is used for reducing dynamic power in sequential circuits. Power is saved by dividing the clock and then distributing the clock to the logic blocks only when there is a need for those blocks to be activated. In this paper, we have optimized dynamic power on ROM using different FPGA families namely Spartan-6, Virtex-7, Artix-7 and Kintex-7 in X-Power Analyzer in both ways i.e. with clock gating and without clock gating technique. So, in this way we have demonstrated the power reduction by using clock gating technique. The whole design is implemented in VHDL and mapped onto Xilinx 14.7.2017-08-25T05:23:31-07:00